Abdelhalim Alsharqawi (Selection)

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6 Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Pipelined SRSL Circuits. ISVLSI 2006: 71-76

5 Abdelhalim Alsharqawi, Abdel Ejnioui: Clockless Pipelining for Coarse Grain Datapaths. VLSI Design 2006: 749-753

4 Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Self-Resetting Stage Logic Pipelines. ISVLSI 2005: 260-262

3 Abdel Ejnioui, Abdelhalim Alsharqawi: Self-resetting stage logic pipelines. ACM Great Lakes Symposium on VLSI 2004: 174-177

2 Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline-Level Control of Self-Resetting Pipelines. DSD 2004: 342-349

1 Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI 2004: 254-257

Selection of 6 from 6 records - Abdelhalim Alsharqawi has 2 coauthors

6		Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Pipelined SRSL Circuits. ISVLSI 2006: 71-76
5		Abdelhalim Alsharqawi, Abdel Ejnioui: Clockless Pipelining for Coarse Grain Datapaths. VLSI Design 2006: 749-753
4		Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Self-Resetting Stage Logic Pipelines. ISVLSI 2005: 260-262
3		Abdel Ejnioui, Abdelhalim Alsharqawi: Self-resetting stage logic pipelines. ACM Great Lakes Symposium on VLSI 2004: 174-177
2		Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline-Level Control of Self-Resetting Pipelines. DSD 2004: 342-349
1		Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI 2004: 254-257