Advances in Automated Source-Level Debugging of Verilog Designs.

Bernhard Peischl Naveed Riaz Franz Wotawa Advances in Automated Source-Level Debugging of Verilog Designs. 363-372 2008 New Challenges in Applied Intelligence Technologies http://dx.doi.org/10.1007/978-3-540-79355-7_35 series/sci/2008-134 db/series/sci/sci134.html#PeischlRW08