BibTeX record phd/it/Solinas09

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@phdthesis{DBLP:phd/it/Solinas09,
  author       = {Marco Solinas},
  title        = {Cache Architectures for Wire-Delay Dominated {CMP} Systems},
  school       = {University of Pisa, Italy},
  year         = {2009},
  url          = {https://etd.adm.unipi.it/theses/available/etd-04162009-145440/},
  timestamp    = {Mon, 08 May 2023 21:43:49 +0200},
  biburl       = {https://dblp.org/rec/phd/it/Solinas09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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