DBLP Record 'journals/vlsisp/WuCSG03'

BibTeX

@article{DBLP:journals/vlsisp/WuCSG03,
  author    = {Xingjun Wu and
               Hongyi Chen and
               Yihe Sun and
               Weixin Gai},
  title     = {A Fully-Pipeline Linear Systolic Architecture for Modular
               Multiplier in Public-Key Crypto-Systems},
  journal   = {VLSI Signal Processing},
  volume    = {33},
  number    = {1-2},
  year      = {2003},
  pages     = {191-197},
  ee        = {http://dx.doi.org/10.1023/A:1021110405895},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}