BibTeX record journals/vlsisp/VanHL16

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@article{DBLP:journals/vlsisp/VanHL16,
  author       = {Lan{-}Da Van and
                  Po{-}Yen Huang and
                  Tsung{-}Che Lu},
  title        = {Cost-Effective and Variable-Channel FastICA Hardware Architecture
                  and Implementation for {EEG} Signal Processing},
  journal      = {J. Signal Process. Syst.},
  volume       = {82},
  number       = {1},
  pages        = {91--113},
  year         = {2016},
  url          = {https://doi.org/10.1007/s11265-015-0988-2},
  doi          = {10.1007/S11265-015-0988-2},
  timestamp    = {Thu, 12 Mar 2020 17:20:07 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/VanHL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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