BibTeX record journals/vlsisp/JiangZCYYS16

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@article{DBLP:journals/vlsisp/JiangZCYYS16,
  author       = {Weiwen Jiang and
                  Qingfeng Zhuge and
                  Xianzhang Chen and
                  Lei Yang and
                  Juan Yi and
                  Edwin Hsing{-}Mean Sha},
  title        = {Properties of Self-Timed Ring Architectures for Deadlock-Free and
                  Consistent Configuration Reaching Maximum Throughput},
  journal      = {J. Signal Process. Syst.},
  volume       = {84},
  number       = {1},
  pages        = {123--137},
  year         = {2016},
  url          = {https://doi.org/10.1007/s11265-015-0984-6},
  doi          = {10.1007/S11265-015-0984-6},
  timestamp    = {Tue, 07 May 2024 20:21:49 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/JiangZCYYS16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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