Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers.

Giuseppe Caire Javier Ventura-Traveset M. Hollreiser Ezio Biglieri Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. 153-168 1995 10 VLSI Signal Processing 2 http://dx.doi.org/10.1007/BF02407033 db/journals/vlsisp/vlsisp10.html#CaireVHB95