Chin-Lung Su Chih-Wea Tsai Cheng-Wen Wu Chien-Chung Hung Young-Shying Chen Ding-Yeong Wang Yuan-Jen Lee Ming-Jer Kao Write Disturbance Modeling and Testing for MRAM. 277-288 2008 16 IEEE Trans. VLSI Syst. 3 http://dx.doi.org/10.1109/TVLSI.2007.915402 db/journals/tvlsi/tvlsi16.html#SuTWHCWLK08