<?xml version="1.0"?>
<dblp>
<article key="journals/tvlsi/SoteriouEWLP07" mdate="2007-11-04">
<author>Vassos Soteriou</author>
<author>Noel Eisley</author>
<author>Hangsheng Wang</author>
<author>Bin Li</author>
<author>Li-Shiuan Peh</author>
<title>Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.</title>
<pages>855-868</pages>
<year>2007</year>
<volume>15</volume>
<journal>IEEE Trans. VLSI Syst.</journal>
<number>8</number>
<ee>http://dx.doi.org/10.1109/TVLSI.2007.900725</ee>
<url>db/journals/tvlsi/tvlsi15.html#SoteriouEWLP07</url>
</article>
</dblp>
