<?xml version="1.0"?>
<dblp>
<article key="journals/tvlsi/SehgalOC06" mdate="2006-08-23">
<author>Anuja Sehgal</author>
<author>Sule Ozev</author>
<author>Krishnendu Chakrabarty</author>
<title>Test infrastructure design for mixed-signal SOCs with wrapped analog cores.</title>
<pages>292-304</pages>
<year>2006</year>
<volume>14</volume>
<journal>IEEE Trans. VLSI Syst.</journal>
<number>3</number>
<ee>http://doi.ieeecomputersociety.org/10.1109/TVLSI.2006.871758</ee>
<url>db/journals/tvlsi/tvlsi14.html#SehgalOC06</url>
</article>
</dblp>
