Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.

Sujan Pandey Manfred Glesner Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. 1111-1124 2007 15 IEEE Trans. VLSI Syst. 10 http://dx.doi.org/10.1109/TVLSI.2007.903924 db/journals/tvlsi/tvlsi15.html#PandeyG07