Yoshiyuki Nakamura Thomas Clouqueur Kewal K. Saluja Hideo Fujiwara Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. 790-800 2007 15 IEEE Trans. VLSI Syst. 7 http://dx.doi.org/10.1109/TVLSI.2007.899235 db/journals/tvlsi/tvlsi15.html#NakamuraCSF07