Sumio Morioka Akashi Satoh A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. 686-691 2004 12 IEEE Trans. VLSI Syst. 7 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2004.830936 db/journals/tvlsi/tvlsi12.html#MoriokaS04