Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.

Valavan Manohararajah Gordon R. Chiu Deshanand P. Singh Stephen Dean Brown Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. 895-903 2007 15 IEEE Trans. VLSI Syst. 8 http://dx.doi.org/10.1109/TVLSI.2007.900744 db/journals/tvlsi/tvlsi15.html#ManohararajahCSB07