BibTeX record journals/tvlsi/LiuLO17

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@article{DBLP:journals/tvlsi/LiuLO17,
  author       = {Yangxurui Liu and
                  Liang Liu and
                  Viktor {\"{O}}wall},
  title        = {Architecture Design of a Memory Subsystem for Massive {MIMO} Baseband
                  Processing},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {25},
  number       = {10},
  pages        = {2976--2980},
  year         = {2017},
  url          = {https://doi.org/10.1109/TVLSI.2017.2732062},
  doi          = {10.1109/TVLSI.2017.2732062},
  timestamp    = {Tue, 07 May 2024 20:24:19 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/LiuLO17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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