BibTeX record: journals/tvlsi/KoBN98

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@article{DBLP:journals/tvlsi/KoBN98,
  author    = {Uming Ko and
               Poras T. Balsara and
               Ashwini K. Nanda},
  title     = {Energy optimization of multilevel cache architectures for {RISC} and
               {CISC} processors},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  year      = {1998},
  volume    = {6},
  number    = {2},
  pages     = {299--308},
  url       = {http://doi.ieeecomputersociety.org/10.1109/92.678891},
  doi       = {10.1109/92.678891},
  timestamp = {Wed, 01 Oct 2014 21:14:37 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/tvlsi/KoBN98},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}