Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.

Tetsuya Iizuka Makoto Ikeda Kunihiro Asada Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. 716-720 2007 15 IEEE Trans. VLSI Syst. 6 http://dx.doi.org/10.1109/TVLSI.2007.898754 db/journals/tvlsi/tvlsi15.html#IizukaIA07