Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.

Jin Guo Antonis Papanikolaou H. Zhang Francky Catthoor Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture. 941-944 2007 15 IEEE Trans. VLSI Syst. 8 http://dx.doi.org/10.1109/TVLSI.2007.900758 db/journals/tvlsi/tvlsi15.html#GuoPZC07