<?xml version="1.0"?>
<dblp>
<article key="journals/tvlsi/FujiwaraNNMMMKY08" mdate="2009-01-31">
<author>Hidehiro Fujiwara</author>
<author>Koji Nii</author>
<author>Hiroki Noguchi</author>
<author>Junichi Miyakoshi</author>
<author>Yuichiro Murachi</author>
<author>Yasuhiro Morita</author>
<author>Hiroshi Kawaguchi</author>
<author>Masahiko Yoshimoto</author>
<title>Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.</title>
<pages>620-627</pages>
<year>2008</year>
<volume>16</volume>
<journal>IEEE Trans. VLSI Syst.</journal>
<number>6</number>
<ee>http://dx.doi.org/10.1109/TVLSI.2008.2000249</ee>
<url>db/journals/tvlsi/tvlsi16.html#FujiwaraNNMMMKY08</url>
</article>
</dblp>
