Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.

Aristides Efthymiou John Bainbridge Douglas A. Edwards Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. 1384-1393 2005 13 IEEE Trans. VLSI Syst. 12 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2005.862722 db/journals/tvlsi/tvlsi13.html#EfthymiouBE05