Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units.

Giorgos Dimitrakopoulos Costas Galanopoulos Christos Mavrokefalidis Dimitris Nikolos Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. 837-850 2008 16 IEEE Trans. VLSI Syst. 7 http://dx.doi.org/10.1109/TVLSI.2008.2000458 db/journals/tvlsi/tvlsi16.html#DimitrakopoulosGMN08