Richard M. Chou Kewal K. Saluja Vishwani D. Agrawal Scheduling tests for VLSI systems under power constraints. 175-185 1997 5 IEEE Trans. VLSI Syst. 2 http://doi.ieeecomputersociety.org/10.1109/92.585217 db/journals/tvlsi/tvlsi5.html#ChouSA97