Switch-factor based loop RLC modeling for efficient timing analysis.

Yu Cao Xiao-dong Yang Xuejue Huang Dennis Sylvester Switch-factor based loop RLC modeling for efficient timing analysis. 1072-1078 2005 13 IEEE Trans. VLSI Syst. 9 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2005.857175 db/journals/tvlsi/tvlsi13.html#CaoYHS05