<?xml version="1.0"?>
<dblp>
<article key="journals/tvlsi/BiswasBDPI06" mdate="2007-03-30">
<author>Partha Biswas</author>
<author>Sudarshan Banerjee</author>
<author>Nikil D. Dutt</author>
<author>Laura Pozzi</author>
<author>Paolo Ienne</author>
<title>ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.</title>
<pages>754-762</pages>
<year>2006</year>
<volume>14</volume>
<journal>IEEE Trans. VLSI Syst.</journal>
<number>7</number>
<ee>http://doi.ieeecomputersociety.org/10.1109/TVLSI.2006.878345</ee>
<url>db/journals/tvlsi/tvlsi14.html#BiswasBDPI06</url>
</article>
</dblp>
