BibTeX record journals/tvlsi/BaiWJGYWLRS23

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@article{DBLP:journals/tvlsi/BaiWJGYWLRS23,
  author       = {Fujun Bai and
                  Song Wang and
                  Xuerong Jia and
                  Yixin Guo and
                  Bing Yu and
                  Hang Wang and
                  Cong Lai and
                  Qiwei Ren and
                  Hongbin Sun},
  title        = {A Low-Cost Reduced-Latency {DRAM} Architecture With Dynamic Reconfiguration
                  of Row Decoder},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {31},
  number       = {1},
  pages        = {128--141},
  year         = {2023},
  url          = {https://doi.org/10.1109/TVLSI.2022.3219437},
  doi          = {10.1109/TVLSI.2022.3219437},
  timestamp    = {Sun, 30 Jul 2023 10:15:43 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/BaiWJGYWLRS23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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