Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.

N. Pete Sedcole Peter Y. K. Cheung Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. 2008 1 TRETS 2 http://doi.acm.org/10.1145/1371579.1371582 db/journals/trets/trets1.html#SedcoleC08