Two-level logic minimization for low power.

Jyh-Mou Tseng Jing-Yang Jou Two-level logic minimization for low power. 52-69 1999 4 ACM Trans. Design Autom. Electr. Syst. 1 http://doi.acm.org/10.1145/298865.298869 db/journals/todaes/todaes4.html#TsengJ99