SapatnekarC00'

BibTeX

@article{DBLP:journals/todaes/SapatnekarC00,
  author    = {Sachin S. Sapatnekar and
               Weitong Chuang},
  title     = {Power-delay optimizations in gate sizing},
  journal   = {ACM Trans. Design Autom. Electr. Syst.},
  volume    = {5},
  number    = {1},
  year      = {2000},
  pages     = {98-114},
  ee        = {http://doi.acm.org/10.1145/329458.329473},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}