A VLSI Layout for a Pipelined Dadda Multiplier

Peter R. Cappello Kenneth Steiglitz A VLSI Layout for a Pipelined Dadda Multiplier ACM Trans. Comput. Syst. 1 2 1983 157-174 http://doi.acm.org/10.1145/357360.357366 db/journals/tocs/tocs1.html#CappelloS83