High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.

Ben A. Abderazek Tsutomu Yoshinaga Masahiro Sowa High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. 3-15 2006 38 The Journal of Supercomputing 1 http://dx.doi.org/10.1007/s11227-006-6719-5 db/journals/tjs/tjs38.html#AbderazekYS06