BibTeX record journals/tie/Li0LNY21

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@article{DBLP:journals/tie/Li0LNY21,
  author       = {Xinying Li and
                  Yan Zhang and
                  Jinjun Liu and
                  Cheng Nie and
                  Yue Yang},
  title        = {A Universal {ZVS} Circuit Design Method for a Family of Interleaved
                  High Step-Up Converters With Least Device Requirement},
  journal      = {{IEEE} Trans. Ind. Electron.},
  volume       = {68},
  number       = {12},
  pages        = {12396--12407},
  year         = {2021},
  url          = {https://doi.org/10.1109/TIE.2020.3047052},
  doi          = {10.1109/TIE.2020.3047052},
  timestamp    = {Thu, 16 Sep 2021 17:58:21 +0200},
  biburl       = {https://dblp.org/rec/journals/tie/Li0LNY21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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