A formal method for hardware IP design and integration under I/O and timing constraints.

Philippe Coussy Emmanuel Casseau Pierre Bomel Adel Baganne Eric Martin A formal method for hardware IP design and integration under I/O and timing constraints. 29-53 2006 5 ACM Trans. Embedded Comput. Syst. 1 http://doi.acm.org/10.1145/1132357.1132359 db/journals/tecs/tecs5.html#CoussyCBBM06