BibTeX record journals/tcas/XuHJY06

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@article{DBLP:journals/tcas/XuHJY06,
  author       = {Jingyu Xu and
                  Xianlong Hong and
                  Tong Jing and
                  Yang Yang},
  title        = {Obstacle-avoiding rectilinear minimum-delay Steiner tree construction
                  toward IP-block-based {SOC} design},
  journal      = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
  volume       = {53-II},
  number       = {4},
  pages        = {309--313},
  year         = {2006},
  url          = {https://doi.org/10.1109/TCSII.2005.862041},
  doi          = {10.1109/TCSII.2005.862041},
  timestamp    = {Thu, 26 Aug 2021 15:41:24 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/XuHJY06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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