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BibTeX record journals/tcas/VudadhaSAS18
@article{DBLP:journals/tcas/VudadhaSAS18, author = {Chetan Vudadha and Ajay Surya and Saurabh Agrawal and M. B. Srinivas}, title = {Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers}, journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.}, volume = {65-I}, number = {12}, pages = {4313--4325}, year = {2018}, url = {https://doi.org/10.1109/TCSI.2018.2838258}, doi = {10.1109/TCSI.2018.2838258}, timestamp = {Fri, 22 May 2020 13:29:50 +0200}, biburl = {https://dblp.org/rec/journals/tcas/VudadhaSAS18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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