BibTeX record journals/tcas/ShahshahaniM20

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@article{DBLP:journals/tcas/ShahshahaniM20,
  author       = {Seyed Mohamad Reza Shahshahani and
                  Hamid Reza Mahdiani},
  title        = {A High-Performance Scalable Shared-Memory {SVD} Processor Architecture
                  Based on Jacobi Algorithm and Batcher's Sorting Network},
  journal      = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
  volume       = {67-I},
  number       = {6},
  pages        = {1912--1924},
  year         = {2020},
  url          = {https://doi.org/10.1109/TCSI.2020.2973249},
  doi          = {10.1109/TCSI.2020.2973249},
  timestamp    = {Thu, 01 Oct 2020 10:56:42 +0200},
  biburl       = {https://dblp.org/rec/journals/tcas/ShahshahaniM20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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