<?xml version="1.0"?>
<dblp>
<article key="journals/tcad/ZhouYCZHCSCSC07" mdate="2008-04-08">
<author>Shuo Zhou</author>
<author>Bo Yao</author>
<author>Hongyu Chen</author>
<author>Yi Zhu</author>
<author>Michael Hutton</author>
<author>Truman Collins</author>
<author>Sridhar Srinivasan</author>
<author>Nan-Chi Chou</author>
<author>Peter Suaris</author>
<author>Chung-Kuan Cheng</author>
<title>Efficient Timing Analysis With Known False Paths Using Biclique Covering.</title>
<pages>959-969</pages>
<year>2007</year>
<volume>26</volume>
<journal>IEEE Trans. on CAD of Integrated Circuits and Systems</journal>
<number>5</number>
<ee>http://dx.doi.org/10.1109/TCAD.2006.885737</ee>
<url>db/journals/tcad/tcad26.html#ZhouYCZHCSCSC07</url>
</article>
</dblp>
