A New Automatic Logic Interconnection Verification System for VLSI Design.

T. Watanabe Makoto Endo N. Miyahara A New Automatic Logic Interconnection Verification System for VLSI Design. 70-82 1983 2 IEEE Trans. on CAD of Integrated Circuits and Systems 2 http://dx.doi.org/10.1109/TCAD.1983.1270023 db/journals/tcad/tcad2.html#WatanabeEM83