DBLP Record 'journals/tcad/WangTJ03'

BibTeX

@article{DBLP:journals/tcad/WangTJ03,
  author    = {Chun-Yao Wang and
               Shing-Wu Tung and
               Jing-Yang Jou},
  title     = {Automatic interconnection rectification for SoC design verification
               based on the port order fault model},
  journal   = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume    = {22},
  number    = {1},
  year      = {2003},
  pages     = {104-114},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2002.805723},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}