BibTeX
@article{DBLP:journals/tcad/ValainisKLS90,
author = {John Valainis and
Sinan Kaptanoglu and
Erwin Liu and
Roberto Suaya},
title = {Two-dimensional IC layout compaction based on topological
design rule checking},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {9},
number = {3},
year = {1990},
pages = {260-275},
ee = {http://doi.ieeecomputersociety.org/10.1109/43.46802},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2006-06-21 by Michael Ley (ley@uni-trier.de)