Takeshi Tokuda Kaoru Okazaki K. Sakashita I. Ohkura T. Enomoto Delay-Time Modeling for ED MOS Logic LSI. 129-134 1983 2 IEEE Trans. on CAD of Integrated Circuits and Systems 3 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28425&arnumber=1270030&count=8&index=0 db/journals/tcad/tcad2.html#TokudaOSOE83