A test evaluation technique for VLSI circuits using register-transfer level fault modeling.

Pradip A. Thaker Vishwani D. Agrawal Mona E. Zaghloul A test evaluation technique for VLSI circuits using register-transfer level fault modeling. 1104-1113 2003 22 IEEE Trans. on CAD of Integrated Circuits and Systems 8 http://doi.ieeecomputersociety.org/10.1109/TCAD.2003.814958 db/journals/tcad/tcad22.html#ThakerAZ03