Timing-Error-Tolerant Network-on-Chip Design Methodology.

Rutuparna Tamhankar Srinivasan Murali Stergios Stergiou Antonio Pullini Federico Angiolini Luca Benini Giovanni De Micheli Timing-Error-Tolerant Network-on-Chip Design Methodology. 1297-1310 2007 26 IEEE Trans. on CAD of Integrated Circuits and Systems 7 http://dx.doi.org/10.1109/TCAD.2007.891371 db/journals/tcad/tcad26.html#TamhankarMSPABM07