Incorporating interconnect, register, and clock distribution delays into the retiming process.

Tolga Soyata Eby G. Friedman James H. Mulligan Jr. Incorporating interconnect, register, and clock distribution delays into the retiming process. 105-120 1997 16 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://doi.ieeecomputersociety.org/10.1109/43.559335 db/journals/tcad/tcad16.html#SoyataFM97