DBLP Record 'journals/tcad/SoyataFM97'

BibTeX

@article{DBLP:journals/tcad/SoyataFM97,
  author    = {Tolga Soyata and
               Eby G. Friedman and
               James H. Mulligan Jr.},
  title     = {Incorporating interconnect, register, and clock distribution
               delays into the retiming process},
  journal   = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume    = {16},
  number    = {1},
  year      = {1997},
  pages     = {105-120},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/43.559335},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}