BibTeX record journals/tcad/SoyataFM97

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@article{DBLP:journals/tcad/SoyataFM97,
  author       = {Tolga Soyata and
                  Eby G. Friedman and
                  James H. Mulligan Jr.},
  title        = {Incorporating interconnect, register, and clock distribution delays
                  into the retiming process},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {16},
  number       = {1},
  pages        = {105--120},
  year         = {1997},
  url          = {https://doi.org/10.1109/43.559335},
  doi          = {10.1109/43.559335},
  timestamp    = {Thu, 24 Sep 2020 11:27:48 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/SoyataFM97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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