Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.

Aviral Shrivastava Ilya Issenin Nikil Dutt Sanghyun Park Yunheung Paek Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. 461-465 2009 28 IEEE Trans. on CAD of Integrated Circuits and Systems 3 http://dx.doi.org/10.1109/TCAD.2009.2013275 db/journals/tcad/tcad28.html#ShrivastavaIDPP09