Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.

Rajeev R. Rao Kaviraj Chopra David T. Blaauw Dennis Sylvester Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. 468-479 2007 26 IEEE Trans. on CAD of Integrated Circuits and Systems 3 http://dx.doi.org/10.1109/TCAD.2007.891036 db/journals/tcad/tcad26.html#RaoCBS07