BibTeX record: journals/tcad/RaghunathanRL00

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@article{DBLP:journals/tcad/RaghunathanRL00,
  author    = {Vijay Raghunathan and
               Srivaths Ravi and
               Ganesh Lakshminarayana},
  title     = {Integrating variable-latency components into high-level synthesis},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  year      = {2000},
  volume    = {19},
  number    = {10},
  pages     = {1105--1117},
  url       = {http://doi.ieeecomputersociety.org/10.1109/43.875270},
  doi       = {10.1109/43.875270},
  timestamp = {Sat, 25 Oct 2014 18:10:56 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/tcad/RaghunathanRL00},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}