@article{DBLP:journals/tcad/RaghunathanRL00,
author = {Vijay Raghunathan and
Srivaths Ravi and
Ganesh Lakshminarayana},
title = {Integrating variable-latency components into high-level
synthesis},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {19},
number = {10},
year = {2000},
pages = {1105-1117},
ee = {http://doi.ieeecomputersociety.org/10.1109/43.875270},
bibsource = {DBLP, http://dblp.uni-trier.de}
}