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@article{DBLP:journals/tcad/PierzynskaP97,
author = {Alicja Pierzynska and
Slawomir Pilarski},
title = {Pitfalls in delay fault testing},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {16},
number = {3},
year = {1997},
pages = {321-329},
ee = {http://doi.ieeecomputersociety.org/10.1109/43.594838},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2006-05-24 by Michael Ley (ley@uni-trier.de)