Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.

Xin Li Jiayong Le Mustafa Celik Lawrence T. Pileggi Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. 1041-1054 2008 27 IEEE Trans. on CAD of Integrated Circuits and Systems 6 http://dx.doi.org/10.1109/TCAD.2008.923241 db/journals/tcad/tcad27.html#LiLCP08