Gershon Kedem Hiroyuki Watanabe Graph-Optimization Techniques for IC Layout and Compaction. 12-20 1984 3 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28427&arnumber=1270052&count=14&index=2 db/journals/tcad/tcad3.html#KedemW84